1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and in particular, to an LDMOS transistor (lateral double-diffusion MOS transistor) and its manufacturing method.
2. Description of the Related Art
There are various applications for semiconductor devices with such circuits as switching regulators and DC/DC converters, and therefore, it has become necessary to increase the output current of semiconductor devices. Thus, LDMOS transistors having a low on-resistance have been drawing attention as possible means to improve the performance of the output current.
LDMOS transistors have a configuration where impurities of a different conductivity type from diffusion areas formed on the surface of a semiconductor substrate are diffused so as to form new diffusion areas and the difference in the length of diffusion in the lateral direction of these diffusion areas is used as the effective channel length. In this configuration, a short channel is formed, and therefore, the structure is appropriate for lowering the on-resistance and increasing the withstand voltage of the drain, as well as for use in various types of drivers, such as LCD drivers, and power supply circuits, and thus, LDMOS transistors have become a key device in fields requiring high power and high withstand voltage.
In general, the performance of LDMOS transistors is measured by the withstand voltage (breakdown voltage) and the on-resistance when turned off. However, there are generally tradeoffs between these two factors, and it is difficult to gain both a high withstand voltage and a low on-resistance at the same time. Therefore, long years of effort have been made to develop an LDMOS transistor where these two factors are both excellent.
The conventional LDMOS transistor described in Japanese Unexamined Patent Publication No. 2004-22769 (hereinafter referred to as well-known Document 1) will be described below with reference to FIG. 19. FIG. 19 is a schematic cross-sectional diagram showing the structure of an N-channel LDMOS transistor formed on a P-type semiconductor substrate.
As shown in FIG. 19, a conventional N-channel LDMOS transistor 100 is provided with a P-type body area 3 and an N-type drift area 5 formed in a position at a distance from this body area 3 in a plane within a P-type semiconductor substrate 1, and furthermore, a high concentration P-type buried diffusion area 4 is formed so as to make contact with the bottom of the body area 3. In addition, the buried diffusion area 4 is formed through implantation under such conditions that the area is buried inside the drift area 5.
An N-type source area 6 and a P-type body contact area 7 having a higher concentration than the body area 3 are formed within the body area 3, and an N-type drain area 8 having a higher concentration than the drift area 5 is formed within the drift area 5. A field oxide film 11 is formed on the drift area 5 so that the drain area 8 and an active area in the drift area 5 are separated. In addition, a gate insulating film 12 is formed so as to cover from the end portion of the source area 6 on the drain side to the end portion of the field oxide film 11 on the source side, and a gate electrode 9 is formed on this gate insulating film 12 and a part of the field insulating film 11.
In addition, a source electrode 6a is formed on the source area 6 and the body contact area 7 so that the source area 6 and the body 3 are electrically connected to the same potential by means of this source electrode 6a. Meanwhile, a drain electrode 8a is formed on the drain area 8.
In the case where the withstand voltage of a general N-channel LDMOS transistor is measured when the transistor is turned off, the source electrode 6a and the gate electrode 9 are set to the GND potential and a positive voltage is applied to the drain electrode 8a. At this time, a reverse bias is applied across the drain area 8 and the source area 6. When a reverse bias is applied between a drain and a source, the electrical field within a depletion layer becomes critical field at a certain voltage, so that avalanche breakdown is caused and a current suddenly starts flowing between the drain and the source. The voltage applied at this time corresponds to the withstand voltage value for the transistor.
FIG. 20 is a schematic cross-sectional diagram showing the structure of a conventional LDMOS transistor in the case where no buried diffusion area 4 as in FIG. 19 is formed. In the conventional LDMOS transistor 101 in FIG. 20, when a reverse bias is applied across the drain and the source, an electrical field is concentrated at the edge of the gate on the drain side (area A in FIG. 20), causing the withstand voltage to lower. Accordingly, it becomes important to mitigate the electrical field at the edge of the gate, in order to increase the withstand voltage. When the electrical field is concentrated in the vicinity of the edge of the gate, a slight amount of charge remains in the gate insulating film, and thus, there is a problem in terms of the reliability, and therefore, it is important to mitigate the electrical field at the edge of the gate, in order to increase the reliability of the transistor.
Thus, in the conventional LDMOS transistor 100 shown in FIG. 19, a buried diffusion area 4 is formed through implantation with higher concentration than in the drift area 5 and with high energy, and provided so as to make contact with the bottom of the body area 3 and be buried within the drift area 5.
In the configuration shown in FIG. 19, when a reverse bias is applied across the drain and the source, a depletion layer extends from the interface in which the P-type buried diffusion area 4 and the N-type drift area 5 are joined. Here, the buried diffusion area 4 has a higher concentration than the drift area 5, and therefore, the depletion layer easily extends toward the drift area 5, and as a result, the entirety of the drift area 5 is substantially depleted. As a result, the electrical field can be sufficiently mitigated in the vicinity of the surface, including at the edge of the gate (area A), and therefore, the concentration in the drift area 5 can be set higher in the case where the same withstand voltage is secured, so that the tradeoff between the withstand voltage and the on-resistance in the device can be greatly lessened.
In addition, Japanese Unexamined Patent Publication No. 07-050413 (hereinafter referred to as well-known Document 2) discloses a method for lessening the tradeoff between the withstand voltage and the on-resistance in devices using an epitaxial layer. FIG. 21 is a schematic cross-sectional diagram showing the structure of the N-channel LDMOS transistor disclosed in well-known Document 2. Here, as the same components as those in FIG. 19 are denoted by the same symbols.
The LDMOS transistor 100a shown in FIG. 21 is provided with a P-type epitaxial layer 102 provided on a P-type semiconductor substrate 1, and a high concentration P-type buried diffusion area 4 formed in the interface between the P-type semiconductor substrate 1 and the P-type epitaxial layer 102.
A P-type body area 3 and a second P-type diffusion area 103 formed so as to provide an excellent electrical connection between the P-type body area 3 and the buried diffusion area 4 are provided within the P-type epitaxial layer 102, and furthermore, a drift area 5 is provided in a position at a distance from the body area 3 in a plane.
In addition, an N-type source area 6 and a body contact area 7 are formed within the body area 3 as with FIG. 19, and an N-type drain area 8 is formed within the drift area 5. In addition, a gate insulating film 12 is formed so as to cover from the end portion of the source area 6 on the drain side to the end portion of the drift area 5 on the source side, and a gate electrode 9 is formed on the gate insulating film 12.
In addition, a source electrode 6a is formed on the source area 6 and the body contact area 7, and the source area 6 and the body area 3 are electrically connected to the same potential by means of the source electrode 6a. Furthermore, a drain electrode 8a is formed on the drain area 8, and a gate plate 15 is formed between the source electrode 6a and the drain electrode 8a. 
The LDMOS transistor 100a in FIG. 21 also has a high concentration P-type buried diffusion area 4 in order to mitigate the electrical field at the edge of the gate (A in the figure), as with the LDMOS transistor 100 in FIG. 19. In addition, the gate plate 15 further mitigates the electrical field, and therefore, in the case where the same withstand voltage is secured, the concentration of the drift area 5 can be set higher, so that the tradeoff between the withstand voltage and the on-resistance in the device can be greatly lessened.
In order to implement the LDMOS transistor described in well-known Document 1 (transistor 100 in FIG. 19), however, it is necessary to form a buried diffusion area 4 through implantation with high energy. In this case, the following problems arise.
FIGS. 22A and 22B are schematic cross-sectional diagrams showing the structure when the buried diffusion area 4 is formed by implanting P-type impurity ions with high energy.
When impurity ions are implanted in order to form the buried diffusion area 4, the implantation area is covered with a resist, so that only the implantation area is exposed and the non-implantation area is masked. FIG. 22A shows a case where the taper angle of the covering resist 16 is 90 degrees relative to the surface of the substrate, and FIG. 22B shows a case where the taper angle is less than 90 degrees, so that the side of the resist 16 is inclined.
In the case where impurity ions are implanted using a resist 16 formed with a taper angle of 90 degrees as a mask, as shown in FIG. 22A, the buried diffusion area 4 can be formed at a desired depth uniformly throughout the entirety of the implantation area. In contrast, when the taper angle is less than 90 degrees, as shown in FIG. 22B, the buried diffusion area 4 can be formed at a desired depth in the area where no resist 16 is formed (area G in the figure), while the buried diffusion area 4 is formed in an area shallower than the desired depth beneath the area where the inclined surface is formed on the resist 16 (area H in the figure). In such cases, as shown in FIG. 22B, a part of the buried diffusion area 4 (area H) rises toward the surface of the substrate.
A described above, the buried diffusion area 4 is formed of a high concentration P-type impurity diffusion area. Meanwhile, the drift area 5 is formed of an N-type impurity diffusion area. Therefore, when a part of the buried diffusion area 4 rises toward the surface, a high concentration P-type impurity diffusion area is formed in a direction approximately perpendicular to the surface of the substrate in the N-type drift area 5, and this area becomes of a high resistance state. Therefore, a problem arises, such that the on-properties when a voltage is applied to the gate electrode 9 greatly deteriorate. Here, although the case where the taper angle is less than 90 degrees, as in FIG. 22B, has been described, the same problems arise even in the case where the taper angle is greater than 90 degrees, that is, in the case where the resist 16 is formed in such a manner that the cross sectional area parallel to the surface of the substrate becomes smaller toward the bottom.
In addition, in the case where the taper angle is 90 degrees, that is, in the case where the resist 16 is formed so that the side is perpendicular to the surface of the substrate, as shown in FIG. 22A, the buried diffusion area 4 does not rise, and thus, there is no such problem as that described above. However, it is necessary to keep the taper angle of the resist 16 stable at 90 degrees during the manufacturing process, and many separate control mechanisms are required in order to do so. Furthermore, even with such control mechanisms, the taper angle in some cases does not remain 90 degrees for a long time, and thus, the structure shown in FIG. 22A is unstable and difficult to implement.
Meanwhile, in the case where the LDMOS transistor 100a described in well-known Document 2 is implemented as shown in FIG. 21, high concentration impurity ions are implanted in the vicinity of the surface of the semiconductor substrate 1 in advance, so that a diffusion area is formed, and after that, an epitaxial layer 102 is grown so that the diffusion area is buried in the epitaxial layer 102, and thus, a buried diffusion area 4 can be formed. Therefore, it is not necessary to implant ions under such conditions that the energy is high in order to form the buried diffusion area 4 at a predetermined depth. Accordingly, unlike in the case of well-known Document 1, high resistance is not provided within the drift area 5 by the rising part of the buried diffusion area 4.
In order to implement the LDMOS transistor described in well-known document 2, however, it is necessary to form an epitaxial layer 102 during the manufacturing process, and therefore, a special epitaxial manufacturing unit becomes necessary, and thus, there is a demerit in terms of the cost, such that the manufacture becomes more expensive.